The Department of Electronics and Communication Engineering at SISTec, Ratibad, successfully organized the VLSI Masters Championship at the Centre of Excellence in Semiconductor Technologies, coordinated by Dr. Yogesh Shrivastava. The competition challenged students through three rigorous rounds, including a VLSI quiz, a buzzer round, and a schematic chip design challenge, testing both knowledge and practical skills.
With access to industry-standard EDA tools through the Chips to Startup (C2S) scheme by MeitY and ChipIN Centre at CDAC Bangalore, students gained hands-on exposure to platforms like Synopsys and Cadence, preparing them for real-world semiconductor design.
Winners:
• Winner – Mr. Deepak Bavne
• First Runner-Up – Mr. Ayush Bele
• Second Runner-Up – Mr. Anand Verma
• Third Runner-Up – Ms. Pooja Malviya
Congratulations to all participants for showcasing exceptional technical talent and innovation.